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HI-15530
5V / 3.3V Manchester Encoder / Decoder
August 2006
GENERAL DESCRIPTION
The HI-15530 is a high performance CMOS integrated circuit designed to meet the requirements of MIL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. The HI-15530 contains both an Encoder and Decoder, which operate independently. The HI-15530 is fully compatible with either 5V or 3.3V logic and transceivers. The device generates MIL-STD-1553 sync pulses, parity bits as well as the Manchester II encoding of the data bits. The decoder recognizes and identifies sync pulses, decodes data bits, and performs parity checking. The HI-15530 supports the 1Mbit/s data rate of MIL-STD1553 over the full temperature and voltage range. For applications requiring small footprints and low cost, the HI-15530 is available in a 24-pin plastic SSOP package. Ceramic DIP and LCC packages are also available to achieve the highest level of reliability and to provide drop-in replacements for obsolete parts from other manufacturers.
FEATURES
! MIL-STD-1553 compatible ! 5V or 3.3V operation ! Interfaces to HI-1567 Transceiver Family ! Small footprint 24-pin plastic SSOP package option ! Direct replacement for: Harris/Intersil HD15530 GEC Plessey Semiconductors MAS15530 Aeroflex ACT15530 ! 1.25 Mbit/s Maximum Data Rate ! Manchester II Encode and Decode ! Sync identification and Lock-in
PIN CONFIGURATION (Top View)
VALID WORD 1 2 3 4 5 6 7 8 9 24 VDD 23 ENCODER CLK 22 SEND CLK IN 21 SEND DATA 20 SYNC SELECT
APPLICATIONS
! MIL-STD-1553 Interfaces ! Smart Munitions ! Stores management ! Sensor interfaces ! Instrumentation
ENCODER SHIFT CLK TAKE DATA SERIAL DATA OUT DECODER CLK BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLK
HI-15530PSI HI-15530PST HI-15530PSM
19 ENCODER ENABLE 18 SERIAL DATA IN 17 BIPOLAR ONE OUT 16 OUTPUT INHIBIT 15 BIPOLAR ZERO OUT 14 6 OUT 13 MASTER RESET
COMMAND / DATA SYNC 10 DECODER RESET 11 GND 12
24 Pin SSOP package
(See page 3-43 for additional Package Pin Configurations)
(DS15530 Rev. G)
HOLT INTEGRATED CIRCUITS www.holtic.com
08/06
HI-15530
PIN DESCRIPTIONS
SIGNAL
VALID WORD ENCODER SHIFT CLOCK TAKE DATA SERIAL DATA OUT DECODER CLOCK BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLOCK COMMAND / DATA SYNC
SECTION
DECODER ENCODER DECODER DECODER DECODER DECODER DECODER DECODER DECODER DECODER
FUNCTION
OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT OUTPUT OUTPUT
DESCRIPTION
A high output signals the receipt of a valid word Shifts data into the encoder on a low to high transition Output is high during receipt of data after identification of a Sync Pulse and two valid Manchester data bits. Received Data output in NRZ format 12x the data rate. Clock for the transition finder and synchronizer, which generates the internal clock for the remainder of the decoder A high input indicates the 1553 bus is in its negative state. This pin must be held high when the Unipolar input is used A high input indicates the 1553 bus is in the positive state. This pin must be held low when the Unipolar input is used Input for unipolar data to the transition finder. Must be held low when Not in use Provides the DECODER CLOCK divided by 12, synchronized by the recovered serial data A high on this pin occurs during the output of decoded data which was preceded by a Command (or Status) synchronizing character. A low output indicates a Data synchronizing character A high applied to this pin during a DECODER SHIFT CLOCK rising edge resets the bit counter 0V supply A high on this pin clears the 2:1 counters in both Encoder and Decoder and resets the divide-by-6 circuit Provides ENCODER CLOCK divided by 6 An active low output intended to drive the zero or negative sense of a MIL-STD-1553 Line Driver A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by forcing them to inactive high states An active low output intended to drive the one or positive sense on a MIL-STD-1553 Line Driver Accepts serial data at the rate of the ENCODER SHIFT CLOCK A high on this pin initiates the encode cycle. (Subject to the preceeding cycle being complete) Actuates a Command Sync for an input high and a Data Sync for a low An active high output which enables the external source of serial Data Clock input at 2 times the Data rate, usually driven by 6 OUT Input to the divide by 6 circuit. Normal frequency is Data rate x12 3.0 V to 5.5 V power supply pin
DECODER RESET GND MASTER RESET 6 OUT BIPOLAR ZERO OUT OUTPUT INHIBIT BIPOLAR ONE OUT SERIAL DATA IN ENCODER ENABLE SYNC SELECT SEND DATA SEND CLOCK IN ENCODER CLOCK VDD
DECODER BOTH BOTH ENCODER ENCODER ENCODER ENCODER ENCODER ENCODER ENCODER ENCODER ENCODER ENCODER BOTH
INPUT POWER INPUT OUTPUT OUTPUT INPUT OUTPUT INPUT INPUT INPUT OUTPUT INPUT INPUT POWER
HOLT INTEGRATED CIRCUITS 2
HI-15530
ENCODER OPERATION
The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide-by-six counter is provided on chip which can be utilized to produce the SEND CLOCK by dividing the ENCODER CLOCK. The Encoder's cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK (1). This cycle lasts for one word length or twenty ENCODER SHIFT CLOCK periods. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high at SYNC SELECT input actuates a command sync or a low will produce a data sync for that word (2). When the Encoder is ready to accept data, the SEND DATA output will go high and remain high for sixteen ENCODER SHIFT CLOCK periods (3). During these sixteen periods the data should be clocked into the SERIAL DATA IN input with every low-tohigh transition of the ENCODER SHIFT CLOCK (3) - (4). After the sync and the Manchester II coded data are transmitted through the BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder adds on an additional bit which is the parity for that word (5). If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (5) as shown to prevent a consecutive word from being encoded. At any time a low on the OUTPUT INHIBIT input will force both bipolar outputs to a high state but will not affect the Encoder in any other way. To abort the Encoder transmission a positive pulse must be applied at MASTER RESET. Anytime after or during this pulse, a low to high transition on SEND CLOCK clears the internal counters and initializes the Encoder for a new word.
MASTER RESET
OUTPUT INHIBIT
SEND CLK IN
6 OUT
BIPOLAR ONE OUT
2 6
Character Former
ENCODER CLK
BIPOLAR ZERO OUT
Bit Counter
SYNC SELECT SEND DATA ENCODER SHIFT CLK SERIAL DATA IN ENCODER ENABLE
FIGURE 1. ENCODER
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER SHIFT CLK ENCODER ENABLE
DON'T CARE
SYNC SELECT
VALID
DON'T CARE
SEND DATA
SERIAL DATA IN BIPOLAR ONE OUT BIPLOAR ZERO OUT (1) (2)
15
14
13
12
11
10
3
2
1
0
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
SYNC
SYNC
15
14
13
12
11
3
2
1
0
P
(3)
(4) (5)
FIGURE 2. ENCODER OPERATION
HOLT INTEGRATED CIRCUITS 3
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. The Manchester II coded data can be presented to the Decoder in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in MIL-STD-1553. The UNIPOLAR DATA input can only accept non-inverted Manchester II coded data (e.g. from BIPOLAR ZERO OUT of an Encoder). The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized (1), the type of sync is indicated on COMMAND/DATA SYNC output. If the sync character was a command sync, this output will go high (2) and remain high for sixteen DECODER SHIFT CLOCK periods (3), otherwise it will remain low. The TAKE DATA output will go high and remain high (2) - (3) while the Decoder is transmitting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in an NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can be shifted into an external register on every low-to-high transition of this clock (2) - (3). After all sixteen decoded bits have been transmitted (3) the data is checked for odd parity. A high on VALID WORD output (4) indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately 20 DECODER SHIFT CLOCK periods after it goes high if not reset low sooner by a valid sync and two valid Manchester bits as shown (1). At any time in the above sequence, a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.
UNIPOLAR DATA IN BIPOLAR ONE IN BIPOLAR ZERO IN SERIAL DATA OUT TRANSITION FINDER CHARACTER IDENTIFIER COMMAND/DATA SYNC TAKE DATA
DECODER CLK MASTER RESET
SYNCHRONIZER
BIT RATE CLK
PARITY CHECK
VALID WORD
DECODER SHIFT CLK DECODER RESET BIT COUNTER
FIGURE 3. DECODER
TIMING
0
1
2
3
4
5
6
7
8
16
17
18
19
DECODER SHIFT CLK BIPOLAR ONE IN BIPLOAR ZERO IN
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
SYNC
SYNC
15
14
13
12
11
10
2
1
0
P
TAKE DATA
COMMAND / DATA SYNC SERIAL DATA OUT
UNDEFINED
15
14
13
12
4
3
2
1
0
VALID WORD
May be high from previous reception
(1)(2)
FIGURE 4. DECODER OPERATION
(3)
(4)
HOLT INTEGRATED CIRCUITS 4
HI-15530
TIMING DIAGRAMS
SEND CLK t E1 ENCODER SHIFT CLK t E2 SERIAL DATA IN VALID VALID t E3
SEND CLK ENCODER SHIFT CLK ENCODER ENABLE t E1 t E4 t E5 VALID t E7 t E6
SYNC SELECT
ENCODER SHIFT CLK SEND DATA
t E8
SEND CLK t E9 BIPOLAR ONE OUT or BIPOLAR ZERO OUT
ENCODER TIMING
DECODER SHIFT CLK t D6 COMMAND / DATA SYNC t D7 TAKE DATA
DECODER SHIFT CLK t D8 SERIAL DATA OUT DATA BIT
DECODER SHIFT CLK t D9 COMMAND / DATA SYNC t D10 TAKE DATA t D11 VALID WORD
DECODER SHIFT CLK t DRH DECODER RESET t DR t DRS
DECODER TIMING
HOLT INTEGRATED CIRCUITS 5
HI-15530
TIMING DIAGRAMS (cont.)
BIT PERIOD BIT PERIOD BIT PERIOD
BIPOLAR ONE IN BIPOLAR ZERO IN
t D1 t D2 t D1
t D3
t D3 t D2
COMMAND SYNC BIPOLAR ONE IN BIPOLAR ZERO IN t D1 t D3 t D1 t D2 DATA SYNC t D2
t D3
BIPOLAR ONE IN t D3 BIPOLAR ZERO IN
t D1 t D1 t D4 ONE
t D3
t D1 t D3 t D3 t D1 t D5 ZERO t D2 t D5 ONE t D4 t D3
UNIPOLAR IN t D2 COMMAND SYNC t D2 UNIPOLAR IN DATA SYNC UNIPOLAR IN t D4 ONE ZERO t D5 t D5
t D2 t D4 t D4 ONE
DECODER TIMING
Bit Period
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19
Command Word
SYNC SYNC
TERMINAL ADDRESS
R/T
SUBADDRESS / MODE
DATA WORD COUNT
P
Data Word
SYNC SYNC
DATA WORD
P
Status Word
SYNC SYNC
TERMINAL ADDRESS
ME
CODE FOR FAILURE MODES
TF
P
MIL-STD-1553 WORD FORMATS
HOLT INTEGRATED CIRCUITS 6
HI-15530
ABSOLUTE MAXIMUM RATINGS
Supply Voltage VDD -0.3V to +7V Power Dissipation at 25C Plastic SSOP Ceramic DIP DC Current Drain per pin Storage Temperature Range: -40C to +85C -55C to +125C 1.5 W, derate10mW/C 1.0 W, derate 7mW/C 10mA -65C to +150C
Voltage at any pin Operating Temperature Range: (Industrial) (Military)
-0.3V to Vcc +0.3V
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.5 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS PARAMETER
Input Voltage Clock Input Voltage Input Leakage Current Output Voltage Input Voltage HI Input Voltage LO Input Voltage HI Input Voltage LO Input Sink Input Source Logic "1" Output Voltage Logic "0" Output Voltage Standby Supply Current Operating Supply Current Input Capacitance Output Capacitance
SYMBOL
VIH VIL VIHC VILC IIH IIL VOH1 VOH2 VOL1 VOL2 IDDSB IDD CIN COUT
CONDITIONS
MIN 70% VDD
TYP
MAX 30% VDD
UNIT
V V V V A A V V
VDD-0.5 0.5V 1.0 -1.0 VDD=5V10%, IOH=-3mA VDD=3.3V10%, IOH=-1mA VDD=5V10%, IOL=1.8mA VDD=3.3V10%, IOH=1mA VIN=VDD, Outputs Open f=1MHz, Outputs Open 2.4 90% VDD 0.4 10% VDD 2.0 10.0 7.0 10.0
V V mA mA pF pF
HOLT INTEGRATED CIRCUITS 7
HI-15530
AC ELECTRICAL CHARACTERISTICS
VDD = 3.0V to 5.5V, GND = 0V, TA = Operating Temperature Range, CL=50pF
PARAMETER Encoder Timing
Encoder Clock Frequency Send Clock Frequency Encoder Clock Rise Time Encoder Clock Fall Time Encoder Data Rate Master Reset Pulse Width Shift Clock Delay Serial Data Setup Time Serial Data Hold Time Enable Setup Time Enable Pulse Width Sync Setup Time Sync Pulse Width Send Data Delay Bipolar Output Delay Enable Hold Time Sync Hold Time
SYMBOL
LIMITS MIN TYP MAX
UNITS
fEC fESC tECR tECF fED tMR tE1 tE2 tE3 tE4 tE5 tE6 tE7 tE8 tE9 tE10 tE11
0 0
15 2.5 8 8
MHz MHz ns ns MHz ns ns ns ns ns ns ns ns
0 150
1.25 125
75 75 90 80 55 150 0 10 95 50 130
ns ns ns ns
Decoder Timing
Decoder Clock Frequency Decoder Clock Rise Time Decoder Clock Fall Time Decoder Data Rate Decoder Reset Pulse Width Decoder Reset Setup Time Decoder Reset Hold Time Master Reset Pulse Width Bipolar Data Pulse Width Sync Transition Span One-Zero Overlap Short Data Transition Span Long Data Transition Span Sync Delay (On) Take Data Delay (On) Serial Data Out Delay Sync Delay (Off) Take Data Delay (Off) Valid Word Delay fDC tDCR tDCF fDD tDR tDRS tDRH tMR tD1 tD2 tD3 tD4 tD5 tD6 tD7 tD8 tD9 tD10 tD11 0 0 0 -20 0 6tDC 12tDC 110 110 80 110 110 110 0 150 75 10 150 tDC+10 18tDC tDC-10 0 15 8 8 1.25 MHz ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
HOLT INTEGRATED CIRCUITS 8
HI-15530
ADDITIONAL PIN CONFIGURATIONS (See page 3-35 for 24-Pin Small Outline SSOP)
SERIAL DATA OUT TAKE DATA ENCODER SHIFT CLK VALID WORD VDD ENCODER CLK SEND CLK IN
VALID WORD 1 ENCODER SHIFT CLK 2 TAKE DATA 3 SERIAL DATA OUT 4 DECODER CLK 5 BIPOLAR ZERO IN 6 BIPOLAR ONE IN 7 UNIPOLAR DATA IN 8 DECODER SHIFT CLK 9 COMMAND / DATA SYNC 10 DECODER RESET 11 GND 12 24 23 22 21 20 19 18 17 16 15 14 VDD ENCODER CLK SEND CLK IN SEND DATA SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT OUTPUT INHIBIT BIPOLAR ZERO OUT 6 OUT
4 3 2 1 28 27 26 25 24
HI-15530CDI HI-15530CDT HI-15530CDM
DECODER CLK N/C N/C BIPOLAR ZERO IN BIPOLAR ONE IN UNIPOLAR DATA IN DECODER SHIFT CLOCK
5 6 7 8 9 10 11
HI-15530CLI HI-15530CLT HI-15530CLM
23 22 21 20
19 12 13 14 15 16 17 18
SEND DATA N/C N/C SYNC SELECT ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT
COMMAND / DATA SYNC DECODER RESET GND MASTER RESET
13 MASTER RESET
24 - Pin Ceramic Side-Brazed DIP
28 - Pin Ceramic LCC
ORDERING INFORMATION HI - 15530PS x x (Plastic)
PART NUMBER LEAD FINISH
Blank F
PART NUMBER
Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE RANGE FLOW BURN IN
I T M
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
15530PS
24 PIN PLASTIC SSOP
See next page for Ceramic package style Ordering Information
HOLT INTEGRATED CIRCUITS 9
BIPOLAR ZERO OUT OUTPUT INHIBIT
6 OUT
HI-15530 ORDERING INFORMATION (cont.) HI - 15530Cx x (Ceramic)
PART NUMBER TEMPERATURE RANGE FLOW BURN IN LEAD FINISH
I T M
PART NUMBER
-40C TO +85C -55C TO +125C -55C TO +125C
PACKAGE DESCRIPTION
I T M
NO NO YES
Gold (Pb-free, RoHS compliant) Gold (Pb-free, RoHS compliant) Tin / Lead (Sn / Pb) Solder
15530CD 15530CL
24 PIN CERAMIC SIDE BRAZED DIP 28 PIN CERAMIC LEADLESS CHIP CARRIER
HOLT INTEGRATED CIRCUITS 10
HI-15530
24-PIN PLASTIC SSOP
Package Type: 24HS
.323 .012 (8.20 .30) .006 TYP (.15) .307 .016 (7.80 .40) .209 .012 (5.30 .30) SEE DETAIL A .012 TYP (.30) .073 .0055 (1.86 .14)
0 to 8 .026 TYP (.65) .030 .008 (.75 .20) DETAIL A
.005 .001 (.13 .08)
24-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 24C
1.220 MAX (30.988 MAX)
.610 .010 (15.494 .254)
.595 .010 (15.113 .254)
.225 MAX (5.715 MAX)
.050 TYP (1.270 TYP)
.085 .009 (2.159 .229)
.600 .010 (15.240 .254)
.125 MIN (3.175 MIN) .018 TYP (.457 TYP)
.100 BSC (2.540 BSC)
.010 +.002/.001 (.254 +.051/.025)
HOLT INTEGRATED CIRCUITS 11
HI-15530
28-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 28S
.020 INDEX (.508 INDEX)
PIN 1
.080 .020 (2.032 .508)
PIN 1
.050 .005 (1.270 .127) .451 .009 (11.455 .229) SQ. .050 BSC (1.270 BSC) .008R .006 (.203R .152) .040 x 45 3PLS (1.016 x 45 3PLS) .025 .003 (.635 .076)
HOLT INTEGRATED CIRCUITS 12

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